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CXD2442Q
Timing Generator for LCD Panels For the availability of this product, please contact the sales office.
Description The CXD2442Q is a timing signal generator for the SVGA LCD panel LCX016 and VGA LCD panel LCX012BL driver. This chip has a built-in serial interface circuit which supports various SVGA and VGA signals as well as double-speed NTSC and PAL signals through external control from a microcomputer, etc. Features * Generates the LCX016/LCX012BL drive pulse. * Supports various SVGA and VGA signals. (LCX016/LCX012BL) LCX016 * Aspect conversion performed at the panel side for the 832 x 624 (Macintosh17), 800 x 600 (SVGA), 640 x 480 (VGA/NTSC), 762 x 572 (PAL), 640 x 400 (PC-98), 832 x 480 (WIDE) modes. * Line double-speed display realized with a built-in double-speed controller. (NTSC/PAL) (Line memory PD485505: NEC) LCX012BL * 640 x 480 (VGA/NTSC/PAL) * Line double-speed display realized with a built-in double-speed controller. (NTSC/PAL) (Line memory PD485505: NEC) * Supports double-speed PAL pulse eliminate. * Supports SVGA pulse eliminate. * Supports PC-98 (640 x 400) line display. * Generates timing signal of external sample-andhold circuit. (for RGB driver and high voltage drive sample and hold) * Supports up/down and/or right/left inversion. * Supports 1H inversion. * AC drive of LCD panels during no signal 80 pin QFP (Plastic)
Applications LCD projectors, etc. Structure Silicon CMOS IC Absolute Maximum Ratings (Ta = 25C, VSS = 0V) * * * * Supply voltage VDD VSS - 0.5 to +7.0 V Input voltage VI VSS - 0.5 to VDD + 0.5 V Output voltage VO VSS - 0.5 to VDD + 0.5 V Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 4.5 to 5.5 * Operating temperature Topr -20 to +75
V C
Note) "Macintosh" is a registered trademark of Apple Computer Inc.. "PC-98" is a registered trademark of NEC. "VGA" is a registered trademark of IBM. Other company names and product names, etc. contained in these materials are trademarks or registered trademarks of the respective companies.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E96537-ST
CXD2442Q
Block Diagram
VDD: 24, 33, 48, 73 VSS: 2, 12, 17, 23, 32, 38, 42, 52, 63, 72
7
PWM
CKI2 3 CKLIM 25 CKI1 11 MASTER CLOCK CKO1 10 DIRECT CLEAR
6
PEO
74 XCLR 75 13 9 PRE TC RPD FPD HDN
PLL PHASE COMPARATOR HSYNC 4 H-SYNC DETECTOR
8 1
68 RSTR PLL COUNTER 69 RCK 70 RSTW DECODER VSYNC 5 V-SYNC SEPARATOR V-RESET PULSE GENERATOR V-CONTROL COUNTER 71 WCK 80 14 15 16 HD SCTR SCLK SDAT
49 RGT 50 SERIAL I/F XRGT
51 MODE3 53 MODE2 54 MODE1
V-POSITION COUNTER BLK 58 VCK 61 VST 62 FLDI 78 FLDO 79 DECODER & V-TIMING PULSE GENERATOR H-POSITION COUNTER
67 DWN 27 XCLP1 28 XCLP2 29 DECODER & H-TIMING PULSE GENERATOR PRG
34 SHD1 35 SHD2
36 SHD3 37 SHD4 39 SH1
PULSE ELIMINATOR FRP 30 XFRP 31 TST1 18 TST2 19 TST3 20 TST4 21 TST5 22 TST6 26 TST7 64 TST8 66 TST9 76 TST10 77 DECODER AUX-VD COUNTER FIELD & LINE CONTROLLER
40 SH2 41 SH3 43 SH4 44 45 46 SH5 SH6 SH7
47 SH8 55 HST 56 HCK1 57 HCK2 59 CLR
60 ENB 65 PCG
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CXD2442Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol HDN Vss CKI2 HSYNC VSYNC PEO PWM FPD RPD CKO1 CKI1 Vss TC SCTR SCLK SDAT Vss TST1 TST2 TST3 TST4 TST5 Vss VDD CKLIM TST6 XCLP1 XCLP2 PRG FRP XFRP Vss VDD I/O O -- I I I I/O I O O I/O I -- I/O I I I -- -- -- -- -- -- -- -- I -- O O O O O -- -- Description Phase comparison pulse output GND Clock input pin (SVGA, VGA) Horizontal sync signal input pin Vertical sync signal input pin Loop filter integrator output pin (AV) Loop filter integrator input pin (AV) Phase comparator output pin (AV) Phase comparator output pin (AV) Oscillation cell output pin (AV) Oscillation cell input pin (AV) GND FPD output pulse width adjustment pin Chip select input pin (serial transfer block) Serial clock input pin (serial transfer block) Serial data input pin (serial transfer block) GND Test pin (Not connected.) Test pin (Not connected.) Test pin (Not connected.) Test pin (Not connected.) Test pin (Connect to GND.) GND Power supply CKI1 input limit pin (High: CKI1 input enabled, Low: Disabled) Test pin (Not connected.) Pedestal clamp pulse 1 output (negative polarity) Pedestal clamp pulse 2 output (negative polarity) Precharge signal pulse output (positive polarity) AC drive inversion timing output AC drive inversion timing output (reverse polarity of FRP) GND Power supply Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- --
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CXD2442Q
Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Symbol SHD1 SHD2 SHD3 SHD4 Vss SH1 SH2 SH3 Vss SH4 SH5 SH6 SH7 SH8 VDD RGT XRGT MODE3 Vss MODE2 MODE1 HST HCK1 HCK2 BLK CLR ENB VCK VST Vss TST7 PCG TST8 DWN
I/O O O O O -- O O O -- O O O O O -- O O O -- O O O O O O O O O O -- -- O -- O
Description Sample-and-hold pulse 1 output (for driver/positive polarity) Sample-and-hold pulse 2 output (for driver/positive polarity) Sample-and-hold pulse 3 output (for driver/positive polarity) Sample-and-hold pulse 4 output (for driver/positive polarity) GND Sample-and-hold pulse 1 output (for high voltage drive sample and hold/positive polarity) Sample-and-hold pulse 2 output (for high voltage drive sample and hold/positive polarity) Sample-and-hold pulse 3 output (for high voltage drive sample and hold/positive polarity) GND Sample-and-hold pulse 4 output (for high voltage drive sample and hold/positive polarity) Sample-and-hold pulse 5 output (for high voltage drive sample and hold/positive polarity) Sample-and-hold pulse 6 output (for high voltage drive sample and hold/positive polarity) Sample-and-hold pulse 7 output (for high voltage drive sample and hold/positive polarity) Sample-and-hold pulse 8 output (for high voltage drive sample and hold/positive polarity) Power supply Right/left inversion discrimination signal output (High: Right, Low: Left) Right/left inversion discrimination signal output (High: Left, Low: Right) Mode switching pin 3 output GND Mode switching pin 2 output Mode switching pin 1 output H start pulse output H clock 1 pulse output H clock 2 pulse output BLK pulse output (positive polarity) CLR pulse output (positive polarity) ENB pulse output (negative polarity) V clock pulse output V start pulse output GND Test pin (Not connected.) PCG pulse output (positive polarity) Test pin (Not connected.) Up/down inversion discrimination signal output (High: Down, Low: Up)
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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CXD2442Q
Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol RSTR RCK RSTW WCK Vss VDD XCLR PRE TST9 TST10 FLDI FLDO HD
I/O O O O O -- -- I I -- -- I O O
Description Reset read output (for high-speed line buffer/negative polarity) Read clock output (for high-speed line buffer) Reset write output (for high-speed line buffer/negative polarity) Write clock output (for high-speed line buffer) GND Power supply System clear pin (Low: All clear) Preset pin (Preset to Macintosh17 mode when Low.) Test pin (Not connected.) Test pin (Not connected.) Field discrimination signal input Field discrimination signal output HD pulse output (positive polarity)
Input pin for open status -- -- -- -- -- -- H H -- -- -- -- -- H: Pull up, L: Pull down
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CXD2442Q
Electrical Characteristics 1. DC characteristics Item Supply voltage Symbol VDD Conditions Min. 4.5 Vss CMOS input 0.7VDD 0.3VDD 2.2 TTL Schmitt trigger input 0.4 0.8VDD CMOS Schmitt trigger input 0.6 IOH = -2mA IOL = 4mA IOH = -4mA IOL = 8mA IOH = -3mA IOL = 3mA 4 6 8 10 12 VDD/2 VDD/2 -10 -40 -40 -40 -100 10 -240 40 40 80 A mA A VDD - 0.8 0.4 V VDD - 0.8 0.4 V V 2 3 CKO1, PEO 5 7 9 11 At a 30pF load 0.2VDD V TC 0.8 V HSYNC VSYNC (VDD = 5.0 0.5V, VSS = 0V, Topr = -20 to + 75C) Typ. 5.0 Max. 5.5 VDD Unit V V V 1 Applicable pins
Input, output voltages VI, Vo Input voltage 1 VIH VIL Vt+ Input voltage 2 Vt- Vt+ - Vt- Vt+ Input voltage 3 Vt- Vt+ - Vt- Output voltage 1 VOH VOL VOH VOL VOH VOL II Input leak current IIL II Output leak current IOZ
Output voltage 2
Output voltage 3
Current consumption IDD
1 PRE, SCLK, SDAT, SCTR, XCLR, FLDI, CKLIM, CKI1, CKO1, CKI2, PWM, PEO 2 MODE1, MODE2, MODE3, HD, HDN, CLR, ENB, PRG, PCG, HST, XCLP1, XCLP2, VST, BLK, FRP, XFRP, VCK, DWN, FLDO, FPD, TC, RPD, RGT, XRGT 3 RSTR, RSTW, RCK, WCK, SH1, SH2, SH3, SH4, SH5, SH6, SH7, SH8, SHD1, SHD2, SHD3, SHD4, HCK1, HCK2 4 Normal input pins (VIN = VSS or VDD) 5 HSYNC, VSYNC, SCLK, SDAT, SCTR, CKI2 6 Pins with pull-up resistors (VIN = VSS) 7 PRE, XCLR, CKLIM 8 Bi-directional pins (input status, VIN = VSS or VDD) 9 CKO1, PEO, TC 10 At high impedance (VIN = VSS or VDD) 11 RPD, FPD 12 fclk = 60MHz, VDD = 5.5V
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CXD2442Q
2. AC characteristics Item Clock input cycle Output rise time Output fall time Cross-point time difference Output rise delay time Output fall delay time HCK1 Duty HCK2 Duty Symbol Applicable pins CKI1 CKI2
(VDD = 5.0 0.5V, Vss = 0V, Topr = -20 to +75C) Min. 28.5 16.6 20 20 -10 10 15 15 48 48 52 52 CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF % ns Typ. Max. Conditions Unit
tr tf
t
All outputs All outputs HCK1, 2 All outputs All outputs HCK1 HCK2
tpr tpf tH/(tH + tL) tL/(tH + tL)
Note) SHP6, 5, 4, 3, 2, 1, 0: LLLLLLL (LSB), HDN4, 3, 2, 1, 0: LLLLL (LSB), SHD2, 1, 0: HHH (LSB), SH2, 1, 0: HLH (LSB) The minimum value for the clock input cycle (CKI2) differs according to the mode used.
3. Serial transfer AC characteristics Symbol Item
(VDD = 5.0 0.5V, Vss = 0V, Topr = -20 to +75C) Min. 4Tns 2Tns 4Tns 2Tns 2Tns 2Tns 5Tns 5Tns T: Master clock cycle (ns) Typ. Max.
ts0 ts1 th0 th1 tw1L tw1H tw2 tw3
SCTR setup time with respect to rise of SCLK SDAT setup time with respect to rise of SCLK SCTR hold time with respect to rise of SCLK SDAT hold time with respect to rise of SCLK SCLK pulse width SCLK pulse width
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CXD2442Q
4. Timing definitions AC characteristics
100% CKI1/2 0V tpr Output 10% 90% tr tf Output 90% tpf 10% VDD 0V VDD 0V VDD
VDD HCK1 50% 50% 0V VDD HCK2 50% 50% 0V t t
HCK1
50% tH
50% tL
50%
Note) HCK2 is the reverse phase of HCK1.
Serial transfer AC characteristics
ts0 SCTR 50% tw1L SCLK 50% ts1 SDAT 50% D15 th1
D14 D9
th0
tw3 50%
tw1H
tw2 50% ts1 D8 th1 D7 D0 D15
Note) See "Serial transfer timing" on P. 14 for the timing relationship between D15 to D0 and each pulse.
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CXD2442Q
Dot Arrangement The LCD panels supported by the CXD2442Q are the LCX016 and the LCX012BL. The dot arrangement is a square arrangement for both panels. The shaded region in the diagram is not displayed, however, for the LCX016, since the CXD2442Q has a built-in display area variable circuit, the number of display area dots varies according to the mode1 to match the various signal protocols. LCX016 Dot Arrangement
Gate SW Gate SW Gate SW
Photo-shielding area
Display area
624 dots
4 dots 832 dots 840 dots 4 dots
1 dot
MODE1 MODE2 MODE3 L L L L H H L L H H L L L H L H L H
Display mode Macintosh17 SVGA PAL VGA/NTSC PC-98 WIDE
Number of horizontal display dots 832 800 762 640 640 832
Number of vertical display dots 624 600 572 480 400 480
Number of display dots 519,168 480,000 435,864 307,200 256,000 399,360 Unit: dot
1 See the description of serial data specifications for details. -9-
1 dot
626 dots
CXD2442Q
LCX012BL Dot Arrangement
Gate SW
Gate SW
Gate SW
Photo-shielding area
Display area
484 dots
5 dots 644 dots 654 dots 5 dots
1 dot
Number of horizontal display dots 644
Number of vertical display dots 484
Number of display dots 311,696 Unit: dot
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1 dot
486 dots
CXD2442Q
Input Signal Protocol 1. Horizontal sync signal a) A standard signal (HSYNC) should be input for the following display modes. LCX016: Macintosh17 (832 x 624), SVGA (800 x 600), VGA/NTSC (640 x 480), PC-98 (640 x 400), PAL (762 x 572), WIDE (832 x 480) LCX012BL: VGA/NTSC/PAL (640 x 480), PC-98 (640 x 400) However, since the CXD2442Q must be combined with a double-speed scan converter (CXD2428Q) for NTSC/PAL double-speed display when not using the built-in double-speed controller, a double-speed (see the CXD2428Q double-speed specifications), 1/2 cycle, 1/2 width horizontal sync signal (HSYNC) should be input as the standard protocol signal. b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL). 2. Vertical sync signal a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal. However, CSYNC is also supported during NTSC/PAL display (when using the built-in double-speed controller) mode. b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL). c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2442Q.
(1) Macintosh17, SVGA, VGA, PC-98, WIDE (LCX016)/VGA, PC-98 (LCX012BL)
HSYNC
VSYNC Sync signal phase reference
(2) Double-speed NTSC (LCX016/LCX012BL)
Double-speed HSYNC VSYNC Sync signal phase reference
(3) Double-speed PAL (LCX016/LCX012BL)
Double-speed HSYNC
VSYNC Sync signal phase reference
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CXD2442Q
(4) NTSC (LCX016/LCX012BL)
ODD FIELD HSYNC VSYNC EVEN FIELD HSYNC VSYNC Sync signal phase reference
(5) PAL (LCX016/LCX012BL)
ODD FIELD HSYNC VSYNC EVEN FIELD HSYNC VSYNC Sync signal phase reference
Notes) (2) and (3) show the timing when using a double-speed scan converter (CXD2428Q). (4) and (5) show the timing when using the built-in double-speed controller (CXD2442Q) and a line memory (PD485505: NEC)
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CXD2442Q
Description of Operation Sync signal input The HSYNC and VSYNC input pins support both separate SYNC and CSYNC. When using the CXD2442Q with CSYNC input, input CSYNC to both pins. (However, CSYNC input is supported only when using the builtin double-speed controller.) Clock input The CXD2442Q has two clock input pin systems to support two types of PLL circuits (1) CKI1 pin A PLL circuit is comprised by the built-in phase comparator and an external VCO circuit. CKI1 is the clock input pin when using this system, and supports the NTSC and PAL double-speed display modes (systems which use the built-in double-speed controller). The PLL clock for this system is adjusted by setting the RPD and FPD transition points so that they fall at the center of the windows as shown in the diagram below. (See the Application Circuit.)
a HSYNC RPD b FPD b Output waveform during PLL lock a
500ns
(2) CKI2 pin This is the clock input pin when using an external PLL IC. The 1/N frequency divider output is output from the HDN pin for the PLL IC. The HDN polarity at this time is set by the serial data HPOL. The HDN width is calculated using the frequency division ratio N/2.
N fH HSYNC HDN N/2 fH fH: Master clock cycle (1 dot) HPOL: L HPOL: H
AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. Horizontal direction pulse The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is dependent on the PLL free running frequency. Vertical direction pulse The number of lines is counted by an internal counter (AUX-VD COUNTER) and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD2442Q, no signal (free running) status is judged if there is no VSYNC input for longer than the following (free running detection) periods. Mode NTSC PAL Other V cycle for no signal Free running detection 263H 313H 650H 468H 900H
Note) NTSC and PAL modes are the modes when using the built-in double-speed controller. - 13 -
CXD2442Q
XCLR pin The CXD2442Q should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. Serial transfer operation 1. Control method The CXD2442Q operation timing is controlled by serial data. The control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise of SCLK. This fetching operation starts from the fall of SCTR and is completed at the next rise of SCTR. Serial Transfer Timing
SCTR
SCLK
SDAT
D15
D14 D13 D12
D11 D10
D9
D8
D7
D6
D5
D4 Data
D3
D2
D1
D0
Address
2. Control data When using the CXD2442Q, set the control data corresponding to each signal source according to the formats in the table below. Address D15 D14 D13 D12 D11D10 D9 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 D7 -- D6 -- D5 -- Data D4 -- D3 -- D2 D1 D0 Function
PLLP10 PLLP9 PLLP8 (A) PLL frequency 1 PLLP7 PLLP6 PLLP5 PLLP4 PLLP3 PLLP2 PLLP1 PLLP0 division ratio (1/N) 0 1 0 1 0 1 0 1 0 1 HP7 VP7 -- -- -- -- -- -- -- -- HP6 VP6 -- HP5 VP5 -- HP4 VP4 HP3 VP3 HP2 VP2 HP1 VP1 HP0 VP0 (B) H-POSITION (C) V-POSITION
HDNP4 HDNP3 HDNP2 HDNP1 HDNP0 (D) HDN-POSITION
SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0 (E) SH-POSITION -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HCKP3 HCKP2 HCKP1 HCKP0 (F) HCK-POSITION HSTP3 HSTP2 HSTP1 HSTP0 (G) HST-POSITION -- -- -- -- CLPP1 CLPP0 (H) CLP-POSITION
SHD2 SHD1 SHD0 SH2 SH1 SH0
MBK2 MBK1 MBK0 MBKB MBKA (I) Mode settings
0 FRP1 FRP0 VPOL HPOL MODE MODE3 MODE2 MODE1 1 CK -- HR -- DWN RGT -- -- HST -- PCG -- DSP PC98 -- -- --
-------- 1
1--
Note) PLLP0, HP0, VP0, HDNP0, SHP0, HCKP0, HSTP0, CLPP0: LSB
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CXD2442Q
Each control data is described in detail below. (A) to (I) (A) PLLP10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The data is 11 bits and the frequency division ratio can be set up to 2045. The actual frequency division ratio should be set as follows. Number of dots for the horizontal period - 2 = Actual number of dots set Examples of settings for major modes are shown below. Examples using the LCX016 1) Macintosh17 (832 x 624) PLLP setting value = 1152 (horizontal period) - 2 1150 (HLLLHHHHHHL: LSB) PLLP Setting data 10 H 9 L 8 L 7 L 6 H 5 H 4 H 3 H 2 H 1 H 0 L
2) SVGA (800 x 600) PLLP setting value = 1000 (horizontal period) - 2 998 (LHHHHHLLHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 H 6 H 5 H 4 L 3 L 2 H 1 H 0 L
3) VGA (640 x 480) PLLP setting value = 896 (horizontal period) - 2 894 (LHHLHHHHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 H 4 H 3 H 2 H 1 H 0 L
4) PC-98 (640 x 400) PLLP setting value = 848 (horizontal period) - 2 846 (LHHLHLLHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 L 4 L 3 H 2 H 1 H 0 L
5) NTSC WIDE (832 x 480) PLLP setting value = 1014 (horizontal period) - 2 1012 (LHHHHHHLHLL: LSB) PLLP Setting data 10 L 9 H 8 H 7 H 6 H 5 H 4 H 3 L 2 H 1 L 0 L
6) NTSC (640 x 480) PLLP setting value = 1560 (horizontal period) - 2 1558 (HHLLLLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 L 7 L 6 L 5 L 4 H 3 L 2 H 1 H 0 L
7) PAL (762 x 572) PLLP setting value = 1880 (horizontal period) - 2 1878 (HHHLHLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 H 7 L 6 H 5 L 4 H 3 L 2 H 1 H 0 L
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CXD2442Q
Examples using the LCX012BL 1) VGA (640 x 480) PLLP setting value = 896 (horizontal period) - 2 894 (LHHLHHHHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 H 4 H 3 H 2 H 1 H 0 L
2) PC-98 (640 x 400) PLLP setting value = 848 (horizontal period) - 2 846 (LHHLHLLHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 L 4 L 3 H 2 H 1 H 0 L
3) NTSC, PAL (640 x 480) PLLP setting value = 1560 (horizontal period) - 2 1558 (HHLLLLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 L 7 L 6 L 5 L 4 H 3 L 2 H 1 H 0 L
(B) HP7, 6, 5, 4, 3, 2, 1, 0 These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of up to 256 dots with 8 bits is possible using the front edge of HSYNC as the reference.
Thp HSYNC
Image display period
Thp: Timing from the edge of HSYNC to the start of image display
Minimum and maximum Thp setting values for each mode LCX016 HP Min. Max. 7 6 5 4 3 2 1 0 832 x 624 800 x 600 762 x 572 640 x 480 640 x 400 832 x 480 HHHHHHHH LLLLLLLL 185 dots 440 dots 153 dots 408 dots 105 dots 360 dots
LCX012BL HP Min. Max. 7 6 5 4 3 2 1 0 644 x 484 HHHHHHHH LLLLLLLL 110 dots 365 dots
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CXD2442Q
(C) VP7, 6, 5, 4, 3, 2, 1, 0 These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of up to 256H with 8 bits is possible using the following references. Non-interlace signal input Front edge of VSYNC Interlace signal input First 1H of VSYNC (Interlace signal input indicates NTSC or PAL double-speed display (using the built-in double-speed controller). In this case, the image is raised or lowered by two lines on the panel side with respect to a 1H adjustment.) (1) Non-Interlace Mode
Tvp Image display period
VSYNC HSYNC Tvp: Timing from the edge of VSYNC to the start of image display
Minimum and maximum Tvp setting values LCX016/LCX012BL VP Min. Max. 7 6 5 4 3 2 1 0 Non-Interlace Mode LLLLLLLL HHHHHHHH 8H 263H
(2) Interlace Mode (a) NTSC
1H
Tvp
Image display period
VSYNC HSYNC (ODD FIELD) HSYNC (EVEN FIELD) Tvp: Timing from the first 1H of the VSYNC edge to the start of image display
Minimum and maximum Tvp setting values LCX016/LCX012BL VP Min. Max. 76543210 LLLLLLLL HHHHHHHH Interlace Mode 4.5H 259.5H - 17 -
CXD2442Q
(b) PAL
1H Tvp Image display period
VSYNC HSYNC (ODD FIELD) HSYNC (EVEN FIELD) Tvp: Timing from the first 1H of the VSYNC edhe to the start of image display
Minimum and maximum Tvp setting values LCX016/LCX012BL VP Min. Max. 76543210 LLLLLLLL HHHHHHHH Interlace Mode 4.5H 259.5H
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CXD2442Q
(D) HDNP4, 3, 2, 1, 0 These bits set the timing for the phase comparison pulse HDN (for the external PLL IC). The phase relationship between the dot clock and the sync signal (HSYNC) is controlled in 3ns (Typ.) units. The control range is 32 positions with 5 bits. Phase control for the SH pulse (SHD4, 3, 2, 1) is also performed at the same time.
3ns (1 x 3ns) HSYNC HDN HCKn SHD1 SHD2 SHD3 SHD4 3ns (1 x 3ns) HDNP4, 3, 2, 1, 0 : LLLLL 0 (decimal) : LLLLH 1 (decimal)
a
a
90ns (30 x 3ns) HSYNC HDN HCKn SHD1 SHD2 SHD3 SHD4 90ns (30 x 3ns) HDNP4, 3, 2, 1, 0 : HHHHL 30 (decimal)
93ns (31 x 3ns)
a
a
: HHHHH 31 (decimal)
Note) The above timings assume SHD2, 1, 0: HHH and HPOL: H (serial data). The value of a is constant regardless of the HDNP setting. n = 1, 2 - 19 -
CXD2442Q
(E) SHP6, 5, 4, 3, 2, 1, 0 These bits control the phase relationship between HCK1, HCK2 and SH1, 2, 3, 4, 5, 6, 7 and 8. The phase can be controlled in 1fH units by the upper 3 bits (SHP6, 5, 4), and in 3ns (Typ.) units by the lower 4 bits (SHP3, 2, 1, 0).
3ns (1 x 3ns) 45ns (15 x 3ns)
HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8
SHP6, 5, 4, 3, 2, 1, 0
: LLLLLLL 0 (decimal)
1fH (1 x 1fH)
: LLLLLLH 1 (decimal)
5fH (5 x 1fH)
: LLLHHHH 15 (decimal)
HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8
SHP6, 5, 4, 3, 2, 1, 0
: LLLLLLL 0 (decimal)
: LLHLLLL 1 (decimal)
: HLHLLLL 5 (decimal)
: HHXXXXX > 5 (decimal)
Note) The above timings assume SH2, 1, 0: HLH (serial data). n = 1, 2
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CXD2442Q
(F) HCKP3, 2, 1, 0 These bits control the phase relationship between the RGB signal and HCK (interlocked with HST) inside the panel, and compensate the HCK delay for the wiring load and scanner, etc. The phase can be controlled to 15 positions (1fH increments) with 4 bits.
HST HCK1 VCKn A A + (1fH x N)
HCKP3, 2, 1, 0
: LLLL
0 (decimal)
: LLLH
1 (decimal)
HST HCK1 VCKn A + (1fH x 14) A: Timing chart timing (design specification value)
HCKP3, 2, 1 ,0
: HHHX > 13 (decimal)
Note) Only HCK and HST are adjusted. The above timings assume HSTP3, 2, 1, 0: LLLH (serial data). (G) HSTP3, 2, 1, 0 These bits control the phase relationship between HCK and HST inside the panel, and compensate the delay difference between HST and HCK for the wiring load and scanner, etc. The phase can be controlled to 12 positions (1fH increments) with 4 bits.
HST HCK1
1fH (1x1fH) HSTP1, 0 : LLLL 0 (dercimal) : LLLH 1 (decimal)
HST HCK1
11fH (11x1fH) HSTP1, 0 : HLHH 11 (decimal)
12fH (12x1fH) : HHXX > 11 (decimal)
Note) The above timings assume RGT: H. The HST polarity is inversed during SVGA (LCX016) mode.
- 21 -
CXD2442Q
(H) CLPP1, 0 These bits adjust the clamp pulse position. The timing can be set to 4 positions with 2 bits, and the adjustment width varies in accordance with each mode.
The centers of the XCLP1 and XCLP2 pulses match.
Wclp1 XCLP1 XCLP2 Wclp2 HST
Tclp1
Tclp2
Macintosh17 (LCX016) CLPP1 L L H H CLPP0 L H L H Tclp1 46 dots 69 dots 92 dots 115 dots Tclp2 23 dots 46 dots 69 dots 92 dots Wclp1 69 dots 69 dots 69 dots 69 dots Wclp2 115 dots 115 dots 115 dots 115 dots HHHHLLHH (243) : LSB HHLHHHLL (220) : LSB HP Limit (HP7, 6, 5, 4, 3, 2, 1, 0) HHHHHHHH (255) : LSB
SVGA (LCX016) CLPP1 L L H H CLPP0 L H L H Tclp1 38 dots 57 dots 76 dots 95 dots Tclp2 19 dots 38 dots 57 dots 76 dots Wclp1 58 dots 58 dots 58 dots 58 dots Wclp2 96 dots 96 dots 96 dots 96 dots HHHHLHHL (246) : LSB HHHLLLHH (227) : LSB HP Limit (HP7, 6, 5, 4, 3, 2, 1, 0) HHHHHHHH (255) : LSB
VGA/NTSC, PAL, PC-98, WIDE (LCX016), VGA, NTSC, PAL (LCX012BL) CLPP1 L L H H CLPP0 L H L H Tclp1 26 dots 39 dots 52 dots 65 dots Tclp2 13 dots 26 dots 39 dots 52 dots Wclp1 38 dots 38 dots 38 dots 38 dots Wclp2 64 dots 64 dots 64 dots 64 dots HHHHHLLL (248) : LSB HHHLHLHH (235) : LSB HP Limit (HP7, 6, 5, 4, 3, 2, 1, 0) HHHHHHHH (255) : LSB
Note) When CLPP1, 0 is set to HL or HH (serial data), the XCLP pulse may not be output due to the internal logic depending on the HP serial data setting value. HP Limit is the upper limit for the serial data HP when setting each mode.
- 22 -
CXD2442Q
(I) Mode settings Mode SHD2 SHD1 SHD0 SH2 SH1 SH0 MBK2 MBK1 MBK0 MBKB MBKA FRP1 FRP0 VPOL HPOL MODE MODE3 MODE2 MODE1 CK HR DWN RGT HST PCG DSP PC98 Input clock switching (High: CKI1, Low: CKI2) External reset switching (High: No reset, Low: Reset) Up/down inversion discrimination signal input (High: Down, Low: Up) Right/left inversion discrimination signal input (High: Right, Low: Left) HST width switching (High: 12 dots wide, Low: 24 dots wide) PCG width switching (High: Main, Low: Sub) Double-speed mode switching (High: Normal, Low: Double-speed) PC-98 (400-line) display switching (High: No display, Low: Display) I-10 I-11 I-12 I-13 I-14 I-8 I-9 Panel display area switching signal input I-7 Pulse eliminate interval switching FRP polarity inversion cycle switching (High: 1F, Low: 2F) FRP polarity inversion cycle switching (High: 1H, Low: F) Input VSYNC polarity switching (High: Positive, Low: Negative) Input HSYNC polarity switching (High: Positive, Low: Negative) Mode switching (High: LCX016 mode, Low: LCX012BL mode) I-6 I-5 I-4 Description Resampling switching (High: Resampling, Low: No resampling) 0.5 bit offset switching (High: No offset, Low: Offset) Overlap switching (High: No overlap, Low: Overlap) 0.5 bit offset switching (High: No offset, Low: Offset) Overlap switching (High: Overlap, Low: No overlap) Overlap width switching (High: 2-dot overlap, Low: 3-dot) Pulse eliminate (FRP) timing switching (High: Main, Low: Sub) Pulse eliminate mode switching (High: SVGA/6, 4 pulse eliminate, Low: PAL/6, 7 pulse eliminate) Pulse eliminate switching (High: No pulse eliminate, Low: Pulse eliminate) I-3 I-2 I-1
- 23 -
CXD2442Q
(I-1) SHD2, 1, 0 These bits set the sample-and-hold pulse (SHD) timing. Set the timing in accordance with each display system.
1fH HCKn SHD1 SHD2 SHD3 SHD4
SHD2, 1, 0
: LLL
: LLH
: LHL
HCKn SHD1 SHD2 SHD3 SHD4
SHD2, 1, 0
: LHH
: HLL
: HLH
HCKn SHD1 SHD2 SHD3 SHD4
SHD2, 1, 0
: HHL
: HHH
Note) The above timings assume HDN4, 3, 2, 1, 0: LLLLL (serial data). n = 1, 2
- 24 -
CXD2442Q
(I-2) SH2, 1, 0 These bits set the sample-and-hold pulse (SH) timing. Set the timing in accordance with each display system.
1fH HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8
SH2, 1, 0
: LLL
: LLH
: LHX
HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8
SH2, 1, 0
: HLL
: HLH
: HHX
Note) The above timings assume SHP6, 5, 4, 3, 2, 1, 0: LLLLLLL (serial data). n = 1, 2
- 25 -
CXD2442Q
(I-3) MBK2, 1, 0, B, A These bits set the pulse eliminate-related mode timings. These timings enable SVGA (scanning line conversion from 600 to 480 vertical lines by 6, 4 pulse eliminate) and double-speed PAL (scanning line conversion from 575 to 480 vertical lines by 6, 7 pulse eliminate) display for the LCX012BL. However, for SVGA display, the horizontal direction is supported by external signal processing. (1) MBK2 This bit sets the FRP-related pulse eliminate timing.
VST VCK FRP HST/PCG ENB MBK2: H (MAIN) MBK2: L (SUB)
(2) MBK1 This bit sets the pulse eliminate mode. Select SVGA or double-speed PAL pulse eliminate mode.
Display start timing VST VCK FRP HST/PCG ENB ODD/EVEN FIELD MBK1: L (double-speed PAL/6, 7 decimation) 123 4567 12345 67 Display start timing
MBK1: H (SVGA/6, 4 decimation)
(3) MBK0 MBK0 H L POSITON No pulse eliminate Pulse eliminate
- 26 -
CXD2442Q
(4) MBK B, A These bits change pulse eliminate timing for each field. These bits determine the pulse eliminate timing for the next 1-field period using the pulse eliminate timing when the field identification pulse (FLDI) is Low as the reference. The optimal pulse eliminate position can be set by setting a pulse eliminate interval of 0 to 3H. The charts below show the pulse eliminate timing for SVGA mode, but the timing is the same for double-speed PAL pulse eliminate.
Display start timing VST VCK Reference timing FRP HST/PCG ENB FLDI L 123 45678
Display start timing VST VCK FRP HST/PCG ENB FLDI H MBK B, A: LL Display start timing VST VCK FRP HST/PCG ENB FLDI H MBK B, A: HL 12 345 678 123 45678
Display start timing
1
234
5678
H MBK B, A: LH Display start timing
123
456
78
H MBK B, A: HH
Note) MBK2: H, MBK1: H, MBK0: L
- 27 -
CXD2442Q
(I-4) FRP1, 0 These bits are the data for switching the LCD AC signal cycle. FRP1, 0 should normally be set to HH.
1H
FRP1, 0: HH (1H/1F inversion) FRP1, 0: LH (1H/2F inversion) FRP1, 0: HL (1F inversion) FRP1, 0: LL (2F inversion)
1F
(I-5) VPOL, HPOL These bits are the data for switching the input SYNC polarity. Sync separation processing is performed with the SYNC polarity fixed to positive by the internal logic. Therefore, the polarity must be switched when the input is positive or negative. Accordingly, when the input SYNC is positive or negative, the VPOL and HPOL data should be set High or Low, respectively. (I-6) MODE This bit switches the HCK, CLR, HST and PCG timing according to the mode. Operation shifts to LCX016 mode when MODE is High, and LCX012BL mode when MODE is Low. Be sure to set this data when using the CXD2442Q in these modes. (I-7) MODE3, 2, 1 These bits switch the panel display area. However, since the panel display area can only be switched for the LCX016, VGA/NTSC mode should be set when using the LCX012BL. When using the LCX016 MODE Macintosh17 (832 x 624) SVGA (800 x 600) PAL (762 x 572) VGA/NTSC (640 x 480) PC-98 (640 x 400) WIDE (832 x 480) When using the LCX012BL MODE VGA/NTSC (640 x 480) Also supports PAL display. - 28 - 1 L 2 H 3 H 1 L L L L H H 2 L L H H L L 3 L H L H L H
CXD2442Q
(I-8) CK This bit switches the input clock. Operation shifts to CKI1 input when CK is High, and CKI2 input when CK is Low. CKI1 input supports only the double-speed NTSC and PAL modes which use the built-in double-speed controller. Therefore, CKI2 input is used for other modes. (I-9) HR This bit controls the input HSYNC-based PLL counter reset operation. (Reset operation is allowed when HR is Low.) Resetting the internal PLL counter at the front edge of the input HSYNC generates an output pulse synchronized to SYNC. This function should be used with systems which do not use a PLL.
Input HSYNC
Reset the internal PLL counter at this timing.
(I-10) DWN, RGT These bits set the up/down and right/left inversion discrimination data. These settings allow display to be performed in accordance with each display system. The sample-and-hold pulse timing supports this right/left inversion function, and SH1, 2, 3 are switched with SH4, 5, 6 and SHD1 with SHD3 by switching between right scan and left scan operation, respectively. See the Timing Charts for details.
(I-11) HST This bit adjusts the HST width.
HST HCK1
12fH
6fH
24fH
HST: H
HST: L
Note) HSTP3, 2, 1, 0: LLLH
- 29 -
CXD2442Q
(I-12) PCG This bit adjusts the PCG width. The PRG and FRP timings are also interlocked at this time.
VCK PRG PCG FRP R1 C1
Note) The VCK transition timing is constant regardless of PCG.
MODE R1 Macintosh17 SVGA PAL VGA/NTSC PC-98 WIDE
PCG = H C1 68 dots 58 dots R1
PCG = L C1 57 dots 48 dots
97 dots 82 dots
86 dots 72 dots
54 dots
38 dots
48 dots
32 dots
- 30 -
CXD2442Q
(I-13) DSP This bit performs the double-speed NTSC and PAL display mode switching settings. Operation shifts to double-speed display mode when DSP is Low. However, DSP should be set High for other modes. This function is only supported when the CXD2442Q's built-in double-speed controller is used. This controller is designed to use the PD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates the double-speed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK (read clock). Operation is as follows. Write operation is started at the RSTW timing, and this memory information is read twice at double speed at the RSTR timing which is delayed by 1/2H and 1H from the RSTW timing. Labeling the master clock frequency (MCK) as f, the write and read clock frequencies at this time are expressed as f/2 and f, respectively. See the specifications for a detailed description of PD485505 operation.
ADC R, G, B IN LINE Mem. PD485505 RSTW WCK HSYNC VSYNC CSYNC CXD2442Q MCK: f Double-speed display system diagram RSTR RCK
DAC
HSYNC RSTW WCK RSTR RCK f f/2
HSYNC
RSTW
RSTR
Double-speed display timing
Note) See the Timing Charts for details. - 31 -
CXD2442Q
(I-14) PC-98 This bit switches the PC-98 (400-vertical line) display mode. Operation shifts to PC-98 mode when PC-98 is Low. However, since this function supports the LCX012BL, PC-98 is normally (modes other than LCX012BL/ PC-98 mode) set High. This function is used to display PC-98 (640 x 400) images in the display area of the LCX012BL (644 x 484). The upper and lower 42 lines outside of the display area are black display during this mode. The vertical high-speed scanning and precharge black writing methods have been introduced as methods for writing these black areas. VCK is shifted to double-speed operation to realize vertical double-speed transfer and enable black display within the limited V blanking. Also, the black level during this period is determined by the PSIG (LCX012BL) level and written at the PCG (LCX012BL pin) timing. At this time, HST is masked, limiting the video signal input.
42 (A)
484
Effective display area (400 lines)
400 (B)
42 (C) 644 Unit: dot
LCX012BL panel
2-line inversion (FRP) Effective display area (B)
VST VCK FRP HST PCG
(A)
(C) : Double-speed scanning black display areas
PC-98/400-line display timing Note) FRP is inversed (panel display) every two lines during double-speed scanning. See the Timing Charts for details.
- 32 -
LCX016 SVGA (Macintosh17) 832 x 624
MODE3/2/1: L/L/L MODE: H DWN: H VP: LLHLLLHH (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD
HDN 620 1 10 624 20 30 38
596
600
610
(BLK)
VST
12
VCK
FRP (1H inversed)
- 33 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
LCX016 SVGA (Macintosh17) _1 832 x 624
Loop Counter: 1152fH MCK f: 57.28MHz (17.46ns)
RGT: H PLLP: HLLLHHHHHHL (LSB) HP: LHHLLHHH (LSB) HDNP: LLLLL (LSB) HP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
1022 64fH
1032
1042
1052
1062
1072
1082
1092
1102
1112
1122
1132
1142
0
10
20
30
40
50
60
70
80
89
32fH
120fH
- 34 -
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 SVGA (Macintosh17) _2 832 x 624
Loop Counter: 1152fH MCK f: 57.28MHz (17.46ns)
RGT: H PLLP: HLLLHHHHHHL (LSB) HP: HLLHHLLL (LSB) HDNP: LLLLL (LSB) HP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
309
224fH
69fH 23fH 23fH 23fH
- 35 -
143fH 97fH 68fH 57fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR 57fH
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 SVGA 800 x 600
MODE3/2/1: H/L/L
MODE: H DWN: H VP: LLHLLHLL (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD
HDN 1 10 20 30 37
594
600
(BLK)
VST
12
VCK
FRP (1H inversed)
- 36 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
LCX016 SVGA 800 x 600
Loop Counter: 1000fH MCK f: 48.00MHz (20.83ns)
RGT: H PLLP: LHHHHHLLHHL (LSB) HP: HHHLHLLL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
970 120fH 56fH
980
990
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
189
24fH
58fH 19fH 19fH 19fH
- 37 -
120fH 82fH 58fH 45fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR 48fH
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 VGA 640 x 480
MODE3/2/1: H/H/L MODE: H DWN: H VP: LLHLLLHH (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD
HDN 640 1 10 20 30 38
614
624
634
(BLK)
VST
12
VCK
FRP (1H inversed)
- 38 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR FRP (1F inversed)
FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
CXD2442Q
LCX016 VGA_1 640 x 480
Loop Counter: 896fH MCK f: 31.33MHz (31.92ns)
RGT: H PLLP: LHHLHHHHHHL (LSB) HP: HLHHHLLL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
706
716
726
736
746
756
766
776
786
796
806
816
826
836
846
856
866
876
886
0
10
20
29
80fH
- 39 -
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 VGA_1 640 x 480
Loop Counter: 896fH MCK f: 31.33MHz (31.92ns)
RGT: H PLLP: LHHLHHHHHHL (LSB) HP: HLHHHLLL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
249
64fH 112fH
120fH 38fH 13fH 13fH 13fH
- 40 -
80fH 32fH 54fH 38fH 29fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 NTSC (ODD) 640 x 480
MODE3/2/1: H/H/L MODE: H DWN: H VP: LLLLHHLL (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: L PC98: H
VSYNC
HSYNC
HD 1 10 20 30 33
HDN
587 588
(BLK)
VST
12
VCK FRP (1H inversed)
HST
- 41 -
ENB
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed)
FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
CXD2442Q
LCX016 NTSC (EVEN) 640 x 480
MODE3/2/1: H/H/L MODE: H DWN: H VP: LLLLHHLL (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: L PC98: H
VSYNC
HSYNC
HD 244 250 260 270 276
HDN
241
243
(BLK)
VST
12
VCK FRP (1H inversed)
HST
ENB
- 42 -
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed)
FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
CXD2442Q
LCX016 NTSC_1 640 x 480
Loop Counter: 1560fH MCK f: 24.54MHz (40.75ns)
RGT: H PLLP: HHLLLLHLHHL (LSB) HP: HHHHLHLH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
1520 115fH 115fH
1530
1540
1550
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
179
37fH
120fH 38fH 13fH 13fH 13fH
- 43 -
80fH 32fH 54fH 38fH 29fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 NTSC_2 640 x 480
Loop Counter: 1560fH MCK f: 24.54MHz (40.75ns)
RGT: H PLLP: HHLLLLHLHHL (LSB) HP: HHHHLHLH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
379
779
788
- 44 -
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 PAL (ODD) 762 x 572
MODE3/2/1: L/H/L MODE: H DWN: H VP: LLLHLLLH (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD 289 300 310 316
HDN
287 288
(BLK)
VST
12
VCK
FRP (1H inversed) HST
ENB
- 45 -
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW
FRP (1F inversed) FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
LCX016 PAL (EVEN) 762 x 572
MODE3/2/1: L/H/L MODE: H DWN: H VP: LLLHLLLH (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD 1 10 20 28
HDN
574
576
(BLK)
VST
12
VCK FRP (1H inversed)
HST
- 46 -
ENB
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
LCX016 PAL_1 762 x 572
Loop Counter: 1880fH MCK f: 29.38MHz (34.04ns)
RGT: H PLLP: HHHLHLHLHHL (LSB) HP: HHLLHHHL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
1800 138fH 44fH 120fH 38fH 13fH
1810
1820
1830
1840
1850
1860
1870
0
10
20
30
40
50
60
70
80
90
100
110
120
130
139
13fH
- 47 -
29fH
80fH 32fH 54fH 38fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 PAL_2 762 x 572
RGT: H PLLP: HHHLHLHLHHL (LSB) HP: HHLLHHHL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H Loop Counter: 1880fH MCK f: 29.38MHz (34.04ns) 300 310 320 330 340 350 359 939
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
948
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 170fH
13fH
HST HCK1 HCK2 SH1 SH2
- 48 -
SH3 SH4 SH5 SH6
SH7 SH8 SHD1 SHD2
SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 NTSC WIDE 832 x 480
MODE3/2/1: H/L/H MODE: H DWN: H VP: LLHLLLHH (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD
HDN 480 1 10 20 30 38
454
460
470
(BLK)
VST
12
VCK
FRP (1H inversed)
- 49 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
CXD2442Q
LCX016 NTSC WIDE_1 832 x 480
Loop Counter: 1014fH MCK f: 31.90MHz (31.35ns)
RGT: H PLLP: LHHHHHHLHLL (LSB) HP: HHHHLHLH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
924 68fH
934
944
954
964
974
984
994
1004
0
10
20
30
40
50
60
70
80
90
100
110
120
129
48fH
120fH 38fH 13fH 13fH 13fH
- 50 -
80fH 29fH
32fH 54fH 38fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 NTSC WIDE_2 832 x 480
Loop Counter: 1014fH MCK f: 31.90MHz (31.35ns)
RGT: H PLLP: LHHHHHHLHLL (LSB) HP: HHHHLHLH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
349
232fH
- 51 -
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 PC-98 640 x 400
MODE3/2/1: L/L/H MODE: H DWN: H VP: LLLHHLHL (LSB) MBK2/1/0/B/A: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD
HDN 400 1 10 20 30 40 37
378
388
(BLK)
VST
12
VCK
FRP (1H inversed)
- 52 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
LCX016 PC-98 640 x 400
Loop Counter: 848fH MCK f: 21.053MHz (47.499ns)
RGT: H PLLP: LHHLHLLHHHL (LSB) HP: HHLHLLHH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
788 64fH 85fH 120fH 38fH 13fH 13fH 13fH
798
808
818
828
838
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
159
59fH
- 53 -
80fH 29fH
32fH 54fH 38fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, HCK1 and 2 are inversed, and pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL VGA 640 x 480
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLHLLLLH (LSB) MBK2/1/0/A/B: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H
VSYNC
HSYNC
HD
HDN 640 1 10 20 30 38
614
624
634
(BLK)
VST
12
VCK
FRP (1H inversed)
- 54 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
CXD2442Q
LCX012BL VGA_1 640 x 480
RGT: H PLLP: LHHLHHHHHHL (LSB) HP: HLHHHHHH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H Loop Counter: 896fH MCK f: 31.333MHz (31.92ns) 876 886 0 10 20 29 756 766 776 786 796 806 816 826 836 846 856 866
706
716
726
736
746
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 80fH
HST HCK1 HCK2 SH1 SH2
- 55 -
SH3 SH4 SH5 SH6
SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL VGA_2 640 x 480
RGT: H PLLP: LHHLHHHHHHL (LSB) HP: HLHHHHHH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H Loop Counter: 896fH MCK f: 31.333MHz (31.92ns) 200 210 220 230 240 249 80 90 100 110 120 130 140 150 160 170 180 190
30
40
50
60
70
64fH 112fH
120fH 13fH 13fH 13fH 38fH
- 56 -
80fH 80fH 32fH 54fH 38fH 29fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL NTSC (ODD) 640 x 480
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLLLHHLL (LSB) MBK2/1/0/A/B: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: L PC98: H
VSYNC
HSYNC
HD 1 10 20 30 33
HDN
485 486
(BLK)
VST
12
VCK FRP (1H inversed)
HST
- 57 -
ENB
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
LCX012BL NTSC (EVEN) 640 x 480
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLLLHHLL (LSB) MBK2/1/0/A/B: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: L PC98: H
VSYNC
HSYNC
HD 244 250 260 270 276
HDN
241
243
(BLK)
VST
12
VCK FRP (1H inversed)
HST
- 58 -
ENB
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
LCX012BL NTSC_1 640 x 480
Loop Counter: 1560fH MCK f: 24.54MHz (40.75ns)
RGT: H PLLP: HHLLLLHLHHL (LSB) HP: HHHHHHLL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
1470 115fH
1480
1490
1500
1510
1520
1530
1540
1550
0
10
20
30
40
50
60
70
80
90
100
110
120
129
37fH 120fH 13fH 38fH 64fH 13fH 13fH
- 59 -
80fH 38fH 29fH
32fH 54fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL NTSC_2 640 x 480
Loop Counter: 1560fH MCK f: 24.54MHz (40.75ns)
RGT: H PLLP: HHLLLLHLHHL (LSB) HP: HHHHHHLL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
329
779
788
115fH
- 60 -
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL PAL (ODD) 640 x 480
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLLHLLHL (LSB) MBK2/1/0/A/B: H/L/L/L/L FRP1/0: H/H VPOL: L DSP: L PC98: H
VSYNC
HSYNC
HD 289 300 310 316
HDN
287
288
(BLK)
VST
12
VCK FRP (1H inversed)
HST
ENB
- 61 -
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
LCX012BL PAL (EVEN) 640 x 480
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLLHLLHL (LSB) MBK2/1/0/A/B: H/L/L/L/L FRP1/0: H/H VPOL: L DSP: L PC98: H
VSYNC
HSYNC
HD 1 10 20 28
HDN
574
576
(BLK)
VST
12
VCK
FRP (1H inversed) HST
- 62 -
ENB
XCLP1
XCLP2
PCG
PRG
CLR
RSTR
RSTW FRP (1F inversed) FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP polarity is not specified.
CXD2442Q
LCX012BL PAL_1 640 x 480
Loop Counter: 1560fH MCK f: 24.38MHz (41.02ns)
RGT: H PLLP:HHLLLLHLHHL (LSB) HP: HHHLHHHH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
1430 115fH
1440
1450
1460
1470
1480
1490
1500
1510
1520
1530
1540
1550
0
10
20
30
40
50
60
70
80
89
37fH 120fH 13fH 38fH
- 63 -
80fH 54fH 38fH 29fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL PAL_2 640 x 480
Loop Counter: 1560fH MCK f: 24.38MHz (41.02ns)
RGT: H PLLP: HHLLLLHLHHL (LSB) HP: HHHLHHHH (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: H HR: H HST: H PCG: H
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
289
779
788
141fH
13fH
13fH
- 64 -
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
32fH
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL PC-98 640 x 400
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLLLLHLL (LSB) MBK2/1/0/A/B: H/H/H/L/L FRP1/0: H/H VPOL: L DSP: H PC98: L
VSYNC
HSYNC
HD
HDN 400 1 10 20 30 40 37
378
388
(BLK)
VST
12
VCK
FRP (1H inversed)
- 65 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
CXD2442Q
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
LCX012BL PC-98 640 x 400
Loop Counter: 848fH MCK f: 21.05MHz (47.50ns)
RGT: H PLLP: LHHLHLLHHHL (LSB) HP: HHLHHLHL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H
788 64fH 85fH 120fH 38fH 13fH 13fH 13fH
798
808
818
828
838
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
159
59fH
- 66 -
80fH 80fH 38fH 29fH
32fH 54fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR
RCK RSTW WCK
CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL SVGA 640 x 480
MODE3/2/1: H/H/L MODE: L DWN: H VP: LLHLLLLH (LSB) MBK2/1/0/A/B: H/H/L/L/L FRP1/0: H/H VPOL: L DSP: H PC98: H HPOL: L
VSYNC
HSYNC
HD
HDN 1 10 20 30 37
594
600
(BLK)
VST
12
VCK
FRP (1H inversed)
- 67 -
HST
ENB
XCLP1
XCLP2
PCG
PRG
CLR
FRP (1F inversed)
FLDO
BLK
Note) When DWN is Low, VST is inversed. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The 1H and 1V cycle FRP and FLDO polarity are not specified.
CXD2442Q
LCX012BL SVGA 640 x 480
Loop Counter: 2048fH > MCK f: 32MHz (31.25ns) > 90 100 110 120 130 140 150 159
RGT: H HP: HHLHHLHL (LSB) HDNP: LLLLL (LSB) SHP: LLLLLLL (LSB) HCKP: LLLL (LSB) HSTP: LLLH (LSB) CLPP: LL (LSB) SHD2/1/0: L/H/H SH2/1/0: H/L/H HPOL: L CK: L HR: H HST: H PCG: H 0 XfH XfH 120fH 13fH 38fH 64fH 13fH 13fH 10 20 30 40 50 60 70 80
XfH
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80fH 80fH 54fH 38fH 29fH
MCK HSYNC (BLK) HD HDN XCLP1 XCLP2 HST HCK1 HCK2 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SH8 SHD1 SHD2 SHD3 SHD4 CLR ENB VCK PRG PCG FRP BLK RSTR 32fH
RCK RSTW WCK CXD2442Q
Note) When RGT is Low, pulses SH1, 2, 3 are switched with SH6, 5, 4, and SHD1 with SHD3. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. The SVGA (LCX012BL) mode timing changes according to the signal processing (H direction) method.
CXD2442Q
Application Circuit
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MODE1
ENB
RGT
VCK
HST
XRGT
HCK1
VST
MODE3
HCK2
TST7
SH7
SH6
SH5
BLK
SH4
VSS
VSS
MODE2
PCG
CLR
SH8
SH3
SH2 40 SH1 39 VSS 38 SHD4 37 SHD3 36 SHD2 35 SHD1 34 VDD 33 VSS 32 XFRP 31 FRP 30 PRG 29 XCLP2 28 XCLP1 27 TST6 26
66 TST8 67 DWN
68 RSTR 69 PD485505 (NEC) 70 RCK RSTW
71 WCK 72 73 74 75 VSS VDD XCLR PRE
76 TST9 77 TST10
78 FLDI 79 FLDO
HSYNC
VSYNC
VDD
SCTR
SCLK
SDAT
PWM
TST1
HDN
TST2
FPD
TST3
CKI2
RPD
TST4
TST5
CKI1
PEO
80
HD
1 Sync signal input
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 +5V 0.1 47 16V +5V +5V 50k 100p 0.01 47 16V
Serial I/F
1M PLL IC IN FB IN CLK 1M 1k 33k +12V OFF 10k ON 1 PRE SET Disable CKI1 INPUT 3.3 16V 0.01 0.01 10 35V Enable 10k 50k 10k 5.1k 0.1 33k
+5V +5V
VDD CKLIM
CKO1
VSS
VSS
TC
VSS
VSS
VSS
1000p L
33k
0.1
C
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD2442Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8
0.12
M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
QFP080-P-1420-A
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0.8 0.2
1
24
16.3

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